求大神帮指导啊！！！编译没问题，但仿真有问题！！！

2019-07-16 00:14发布

tica, Arial, sans-serif">module zhen_jing(pi_clk,rst_n,cout);
input pi_clk;
input rst_n;
output reg[7:0]  cout;
reg [19:0]  div_cnt;
reg       clk_c;
reg       div_end;

parameter d_size=19'd499999;

//分频
always@(posedge pi_clk or negedge rst_n)
begin
   if(!rst_n)
      begin
         div_cnt<=0;
         clk_c<=0;
      end
   else
      begin
      if(div_cnt==d_size)
         begin
         clk_c<=~clk_c;
         div_cnt<=0;
         end
      else
      div_cnt<=div_cnt+1'b1;
      end

end

//计数
always@(negedge clk_c or negedge rst_n)
   if(!rst_n)
   cout<='d0;
   else if(div_end)
   begin
      cout<=cout+1'b1;
      if(cout==8'd255)
      div_end<=1'b0;
      else
      div_end<=1'b1;
   end
   else
   begin
      cout<=cout-'d51;
      if(cout==0)
      div_end<=1'b1;
      else
      div_end<=1'b0;
   end

endmodule

`timescale 1ns/1ns
module tb_zhen_jing;
reg clk,clr,clk_r;
wire cout_c;

initial
  begin
            clk<=0;
            clr<=0;
      #30 clr<=1;
  end

always #10 clk<=~clk;

zhen_jing    zhen_jing_inst(
            .pi_clk(clk),
            .rst_n(clr),
            .clk_c(clk_r),
            .cout(cout_c)
);

endmodule

编译没问题，但仿真有问题，问题如下，求指导啊
** Error: (vsim-3389) D:/project/sim/tb_zhen_jing.v(21): Port 'clk_c' not found in the connected module (3rd connection).
#
#       Region: /tb_zhen_jing/zhen_jing_inst
# ** Fatal: (vsim-3365) D:/project/sim/tb_zhen_jing.v(21): Too many port connections. Expected 3, found 4.
# Time: 0 ns  Iteration: 0  Instance: /tb_zhen_jing/zhen_jing_inst File: D:/project/design/zhen_jing.v
# FATAL ERROR while loading design
# Error loading design

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