library ieee;
use ieee.std_logic_1164.all;
entity channel is
  port(
       convert_start: in std_logic;
       ADDR: out std_logic_vector(2 downto 0);
       keyboard: in std_logic_vector(2 downto 0) );
  end entity;
architecture behavior of channel is
  signal d_ADDR:std_logic_vector(2 downto 0);
  begin
  d_ADDR<=keyboard;
process(convert_start)
  begin
  if(convert_start'event and convert_start='1')
  then ADDR<=d_ADDR;
  end if;
end process ;
end behavior;
C:UsersAdministratorDesktop u.png