仿真正确  波形文件产生不了波形  求解

module snatch(A,B,C,D,clk,reset,out);//light and answering
input A,B,C,D;
input reset,clk;
wire [3:0]key;
//output [3:0]led0;
//output [2:0]led1;
output [3:0]out;
assign led0={alARM,s};//warning sb cheat
assign led1={c,s};//answer
assign key=reset?{D,C,B,A}:0;//who responde firstly
reg[1:0]s;
reg c;
reg[2:0] count;
reg[3:0]out;
reg [1:0]alarm;
always@(posedge clk)
  if(!reset)
begin
    begin
  count<=0;
    s<=0;c<=0;alarm<=0;end
     if(A || B || C || D)//alarm sb breaking rule
       begin alarm<=2'b11; end  end
  else
begin
if (count==4)
    begin c<=1;count<=0;end
else count<=count+1;//beging answering
end


always@(posedge clk)
case(key)//judge which input  assign led0={alarm,s};
4'b0001:s<=2'b00;//A
4'b0010:s<=2'b01;//B
4'b0100:s<=2'b10;//C
4'b1000:s<=2'b11;//D
//default:s<=2'bzz;//other
endcase

always@(posedge clk)
case(led0)//warning sb cheat
4'b1100: out<=4'b0001;//A light
4'b1101: out<=4'b0010;//B light
4'b1110: out<=4'b0100;//C light
4'b1111: out<=4'b1000;//D light
//default:out<=4'b0000;
endcase

always@(posedge clk)
case(led1)  //judge which light assign led1={c,s};
3'b100:out<=4'b0001;//A light
3'b101:out<=4'b0010;//B light
3'b110:out<=4'b0100;//C light
3'b111:out<=4'b1000;//D light
//default:out<=4'b0000;
endcase

endmodule