谁能帮我看看这个错误怎么解决啊 - 平头弟

谁能帮我看看这个错误怎么解决啊

2019-07-16 01:08发布

站内问答 / FPGA

2001 1

module encrypt_engine(
input wire i_clk,
input wire i_rst_n,
input wire i_encrypty_en,

input wire i_send_random_done,
output reg o_req_send_random,
output reg [511:0]om_random,

input wire i_rrandom_done,
output reg o_req_rrandom,
input wire [511:0]im_back_random,

input wire i_cal_mac_done,
output reg o_reg_cal_mac,

input wire i_rmac_done,
output reg o_reg_rmac,
input wire [159:0]expected_mac,

output reg o_enable
);

parameter PARA_SECRET =64'ha8a7a6a5a4a3a2a1;    //set secret value
//parameter PARA_SECRET =64'h0000000000000000;    //set secret value
parameter PARA_CV=160'h67452301EFCDAB8998BADCFE10325476C3D2E1F0;

parameter IDLE                =4'h0;
parameter STATE_SEND_RANDOM    =4'h1;
parameter STATE_WAIT1          =4'h2;
parameter STATE_READ_RANDOM    =4'h3;
parameter STATE_WAIT3          =4'h4;
parameter STATE_SEND_CAL_CMD    =4'h5;
parameter STATE_WAIT2          =4'h6;
parameter STATE_READ_MAC       =4'h7;
parameter STATE_SHA1_WR_CMD    =4'h8;
parameter STATE_SHA1_WR_DATA    =4'h9;
parameter STATE_COMP          =4'ha;
parameter GEN_RANDOM          =4'hb;

parameter SHA1_LOADIN_NUM       =6'D15;
parameter PARA_WAIT1_NUM       =20'h3d090;
parameter PARA_WAIT2_NUM       =20'h3d090;
parameter PARA_WAIT3_NUM       =20'h3d090;

reg[3:0]  current_state;
reg[3:0]  next_state;

reg[19:0] wait1_cnt;
reg[19:0] wait2_cnt;
reg[19:0] wait3_cnt;
reg[7:0] gen_random_cnt;

reg[5:0] wr_data_cnt;
wire[511:0] w_sha1_data_in_reverse;
reg[31:0] sha1_data_in;
reg[511:0] sha1_data_in_buf;
reg[2:0] cmd_i;
reg cmd_w_i;
wire[3:0] cmd_o;
wire[159:0] SHA1_result;
wire[31:0] text_o;
wire[7:0] rng_byte;
//assign                                           om_random                            =
{8'h3f,8'h3e,8'h3d,8'h3c,8'h3b,8'h3a,8'h39,8'h38,8'h37,8'h36,8'h35,8'h34,8'h33,8'h32,8'h31,8'h30,
//
8'h2f,8'h2e,8'h2d,8'h2c,8'h2b,8'h2a,8'h29,8'h28,8'h27,8'h26,8'h25,8'h24,8'h23,8'h22,8'h21,8'h20,
//
8'h1f,8'h1e,8'h1d,8'h1c,8'h1b,8'h1a,8'h19,8'h18,8'h17,8'h16,8'h15,8'h14,8'h13,8'h12,8'h11,8'h10,
//
8'h0f,8'h0e,8'h0d,8'h0c,8'h0b,8'h0a,8'h09,8'h08,8'h07,8'h06,8'h05,8'h04,8'h03,8'h02,8'h01,8'h00};
assign w_sha1_data_in_reverse={8'hb8,8'h01,8'h00,8'h00,
                           8'h00,8'h00,8'h00,8'h00,
                           8'h80,om_random[439:416],
                           PARA_SECRET[63:32],
                           om_random[382:32],
                           PARA_SECRET[31:0]};
always@(negedge i_rst_n or posedge i_clk)
begin
if(~i_rst_n)
o_req_send_random<=0;
else if(i_send_random_done)
o_req_send_random<=0;
else if(current_state==STATE_SEND_RANDOM)
o_req_random<=1;
end

always@(negedge i_rst_n or posedge i_clk)
begin
if(~i_rst_n)
o_req_rrandom<=0;
else if(i_rrandom_done)
o_req_send_random<=0;
else if(current_state==STATE_READ_RANDOM)
o_req_random<=1;
end

always@(negedge i_rst_n or posedge i_clk)
begin
if(~i_rst_n)
o_req_cal_mac<=0;
else if(i_cal_mac_done)
o_req_cal_mac<=0;
else if(curent_state==STATE_CAL_CMD)
o_req_cal_mac<=1;
end

always@(negedge i_rst_n or posedge i_clk)
begin
if(~i_rst_n)
o_req_rmac<=0;
else if(i_rmac_done)
o_req_rmac<=0;
else if(current_state==STATE_READ_MAC)
o_req_rmac<=1;
end
//*********************************************
//atate_machine
//*********************************************
always @(negedge i_rst_n or posedge i_clk)
begin
if(~i_rst_n)
current_state <=IDLE;
else
current_state <=next_state;
end

always@(*)
begin
case(curent_state)
IDLE:
if(i_encrypty_en)
next_state=GEN_RANDOM;
else
next_state=current_state;
GEN_RANDOM:
if(gen_random_cnt>=8'd100)
next_state=STATE_SEND_RANDOM;
else
next_state=GEN_RANDOM;
STATE_SEND_RANDOM:
if(i_send_random_done)
next_state=STATE_WAIT1;
else
next_state =current_state;
STATE_WAIT1:
if(wait1_cnt>=PARA_WAIT1_NUM)
next_state =STATE_READ_RANDOM;
else
next_state=current_state;
STATE_READ_RANDOM:
if(i_rrandom_done)
next_state =STATE_WAIT3;
else
next_state=current_state;
STATE_WAIT3:
if(wait1_cnt>=PARA_WAIT3_NUM)
next_state =STATE_SEND_CAL_CMD;
else
next_state=current_state;
STATE_SEND_CAL_CMD:
if(i_rrandom_done)
next_state =STATE_WAIT2;
else
next_state=current_state;
STATE_WAIT2:
if(wait1_cnt>=PARA_WAIT2_NUM)
next_state =STATE_READ_MAC;
else
next_state=current_state;
STATE_READ_MAC:
if(i_rmac_done)
next_state =STATE_SHA1_WR_CMD;
else
next_state=current_state;
STATE_SHA1_WR_CMD:
next_state =STATE_SHA1_WR_DATA;
STATE_SHA1_WR_DATA:
if(wr_data_cnt>=4'hf)
next_state =STATE_COMP;
else
next_state=current_state;
STATE_COMP:
next_state=current_state;
default:next_state =IDLE;
endcase
end

sha1 sha_core(
.i_clk          (i_clk ),
.i_rst          (i_rst_n ),
.im_text          (sha1_data_in ),
.im_cmd          (cmd_i ),
.im_cmd_w       (cmd_w_i ),
.om_text          (text_o ),
.om_cmd          (com_o ),
.om_SHA1_result (SHA1_result )
);

rng_8bits u_rng_8bits(
.i_clock          (i_clk ),
.i_reset          (!i_rst_n ),
.om_rng_byte    (rng_byte)
);

always @(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
gen_random_cnt<=0;
else if (current_state==GEN_RANDOM&&gen_random_cnt<=8'd100)
gen_random_cnt<=gen_random_cnt+8'h1;
else if(current_state==GEN_RANDOM)
gen_random_cnt<=gen_random_cnt;
else
gen_random_cnt<=0;
end

always@(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
om_random<=0;
else if(current_state==GEN_RANDOM)
om_random<={om_random[503:0],rng_byte};
else
om_random<=om_random;
end

always@(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
begin
sha1_data_in<=0;
sha1_data_in_buf<=0;
end
else if(current_state==STATE_SHA1_WR_DATA)
begin
if(wr_data_cnt==6'h0)
begin
sha1_data_in <=
{w_sha1_data_in_reverse[7:0],w_sha1_data_in_reverse[15:8],w_sha1_data_in_reverse[23:16],w_sha1_data_in_reverse[31:24]};
sha1_data_in_buf<=w_sha1_in_reverse[511:32];
end
else
begin
sha1_data_in<=
{sha1_data_in_buf[7:0],sha1_data_buf[15:8],sha1_data_in_buf[23:16],sha1_data_buf[31:24]};
                     sha1_data_in_buf<=sha1_data_in_buf[511:32];
                     end
            end
else
begin
sha1_data_in<=0;
sha1_data_in_buf<=0;
end
end

always@(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
begin
cmd_i<=0;
cmd_w_i=0;
end
else if(current_state==STATE_SHA1_WR_CMD)
begin
cmd_i<=2'b10;
cmd_w_i<=1'b1;
end
else
begin
cmd_i<=0;
cmd_w_i<=0;
end
end

always @(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
wr_data_cnt<=0;
else if(current_state==STATE_SHA1_WR_DATA)
wr_data_cnt<=wr_data_cnt+1'b1;
else
wr_data_cnt<=0;
end

always @(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
wait1_cnt<=0;
else if(current_state==STATE_WAIT1)
begin
if(wait1_cnt>=PARA_WAIT1_NUM)
wait1_cnt<=wait1_cnt;
else
wait1_cnt<=0;
end

always @(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
   wait2_cnt<=0;
else if(current_state==STATE_WAIT2)
begin
if(wait2_cnt>=PARA_WAIT2_NUM)
   wait2_cnt<=wait2_cnt;
else
   wait2_cnt<=wait2_cnt+1'b1;
  end
else
wait2_cnt<=0;
end

always @(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
wait3_cnt<=0;
else if(current_state==STATE_WAIT3)
begin
if(wait3_cnt>=PARA_WAIT3_NUM)
wait3_cnt<=wait3_cnt;
else
wait3_cnt<=wait3_cnt+1'b1;
end
else
wait3_cnt<=0;
end

always @(posedge i_clk or negedge i_rst_n)//compare mac p a r e
begin
if(!i_rst_n)
o_enable<=0;
else if(current_state == STATE_COMP &&(cmd_o == 4'b0000)&& SHA1_result ==expected_mac)
o_enable<=1'b1;
else
o_enable<=o_enable;
end

endmodule

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1条回答

1楼-- · 2019-07-16 04:42

Error (10170): Verilog HDL syntax error at encrypt_engine.v(65) near text "{";  expecting an identifier, or "endmodule", or a parallel statement
Error (10170): Verilog HDL syntax error at encrypt_engine.v(298) near text "always";  expecting ";", or "@", or "end", or an identifier ("always" is a reserved keyword ), or a system task, or "{", or a sequential statement
Error (10170): Verilog HDL syntax error at encrypt_engine.v(313) near text "always";  expecting ";", or "@", or "end", or an identifier ("always" is a reserved keyword ), or a system task, or "{", or a sequential statement
Error (10170): Verilog HDL syntax error at encrypt_engine.v(328) near text "always";  expecting ";", or "@", or "end", or an identifier ("always" is a reserved keyword ), or a system task, or "{", or a sequential statement
Error (10170): Verilog HDL syntax error at encrypt_engine.v(338) near text "endmodule";  expecting ";", or "@", or "end", or an identifier ("endmodule" is a reserved keyword ), or a system task, or "{", or a sequential statement

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