module dd(clk,RS,RW,E,Data);
input clk;//50MHZ时钟的输入
output RS,RW,E;//1602的控制信号使能,数据/命令,读/写
output [7:0]Data;//数据端
reg RS;
reg [7:0]Data;
parameter address=8'h80;//第一行
parameter address2=8'hc0;//第二行
assign RW=1'b0;//只用显示时,一直是写的状态
reg clk_e;
reg [15:0]count;
always @(posedge clk)
begin
count=count+1'b1;
if(count==16'd50000)
begin
clk_e=~clk_e;//作为使能端
count=16'd0;
end
end
reg[27:0]cnt2;
reg[3:0]cnt1;
always @(posedge clk_e)
if(cnt2==25000000)begin cnt1<=cnt1+1'b1;cnt2<=28'd0;end
else if(cnt1>=9)cnt1<=4'd1;
else cnt2<=cnt2+1'b1;
reg [1:0]jishu;
reg [4:0]zhuangtai;//状态机状态
reg temp;
always @(posedge clk_e)
begin
case(zhuangtai)
5'b00000:begin
temp<=1'b0;
RS<=1'b0;
Data<=8'h38;//显示模式设置
zhuangtai<=zhuangtai+1'b1;
end
5'b00001:begin
RS<=1'b0;
Data<=8'h0c;//显示开及光标设置
zhuangtai<=zhuangtai+1'b1;
end
5'b00010:begin
RS<=1'b0;
Data<=8'h06;//显示光标移动设置
zhuangtai<=zhuangtai+1'b1;
end
5'b00011:begin
RS<=1'b0;
Data<=8'h01;//显示清屏
zhuangtai<=zhuangtai+1'b1;//前面几个状态是初始化的状态
end
5'b00100:begin
RS<=1'b0;
Data<=address;//设置显示起始地址,第一行起始位置开始显示
zhuangtai<=zhuangtai+1'b1;
end
5'b00101:begin
RS<=1'b1;
Data<={4'b0011,cnt1[3:0]};
zhuangtai<=zhuangtai+1'b1;
end
5'b00110:begin
RS<=1'b1;
Data<="a";
zhuangtai<=zhuangtai+1'b1;
end
5'b00111:begin
RS<=1'b1;
Data<="x";
zhuangtai<=zhuangtai+1'b1;
end
5'b01000:begin
RS<=1'b1;
Data<="i";
zhuangtai<=zhuangtai+1'b1;
end
5'b01001:begin
RS<=1'b1;
Data<="7";
zhuangtai<=zhuangtai+1'b1;
end
5'b01010:begin
RS<=1'b1;
Data<="7";
zhuangtai<=zhuangtai+1'b1;
end
5'b01011:begin
RS<=1'b1;
Data<="7";
zhuangtai<=zhuangtai+1'b1;
end
5'b01100:begin
RS<=1'b1;
Data<="!";
zhuangtai<=zhuangtai+1'b1;
end
5'b01101:begin
RS<=1'b0;
Data<=address2;//切换到第二行显示
zhuangtai<=zhuangtai+1'b1;
end
5'b01110:begin
RS<=1'b1;
Data<="7";
zhuangtai<=zhuangtai+1'b1;
end
5'b01111:begin
RS<=1'b1;
Data<="7";
zhuangtai<=zhuangtai+1'b1;
end
5'b10000:begin
RS<=1'b1;
Data<=":";
zhuangtai<=zhuangtai+1'b1;
end
5'b10001:begin
RS<=1'b1;
Data<="2";
zhuangtai<=zhuangtai+1'b1;
end
5'b10010:begin
RS<=1'b1;
Data<="0";
zhuangtai<=zhuangtai+1'b1;
end
5'b10011:begin
RS<=1'b1;
Data<="3";
zhuangtai<=zhuangtai+1'b1;
end
5'b10100:begin
RS<=1'b1;
Data<="7";
zhuangtai<=zhuangtai+1'b1;
end
5'b10101:begin
RS<=1'b1;
Data<="6";
zhuangtai<=zhuangtai+1'b1;
end
5'b10110:begin
RS<=1'b1;
Data<="9";
zhuangtai<=zhuangtai+1'b1;
end
5'b10111:begin
RS<=1'b1;
Data<="7";
zhuangtai<=zhuangtai+1'b1;
end
5'b11000:begin
RS<=1'b1;
Data<="8";
zhuangtai<=zhuangtai+1'b1;
end
5'b11001:begin
RS<=1'b1;
Data<="8";
zhuangtai<=zhuangtai+1'b1;
end
5'b11010:begin
temp<=1'b1;//最后使能端一直拉高
zhuangtai<= 5'b00100;
Data<=8'bz;
end
default zhuangtai<=4'b0000;
endcase
end
reg D1,D2,D3,D4,D5;
always @(posedge clk)
begin
D1<=clk_e;
D2<=D1;
D3<=D2;
D4<=D3;
D5<=D4;
end
assign E=D5|temp;
endmodule
大家看看 5'b00101:begin
RS<=1'b1;
Data<={4'b0011,cnt1[3:0]};
zhuangtai<=zhuangtai+1'b1;
end
为什么cnt1显示的数一直为0,而不是1,2,3,4.。。。呢?
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