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module rx(clk,rxd,rd,ce,data,error,rdc);input clk,rxd;//clk=11.0592MHzinput rd,ce;output error,rdc; //rdc--receive datacompletedoutput [7:0] data;
reg [4:0] t;reg [3:0] s;reg [7:0] data; reg [7:0] data0,data1;reg error,rdc;reg rdf; //rdf--read data flagalways @(ce or rd)if((ce && rd) ==1 ) begin data= data1;       rdf=1;  endelse begin data=8'hzz;       rdf=0;  endalways @(posedge clk)          //baud=921.6khzbegin  if(rdf==1)rdc<=0; case(s)  0:if(rxd==1)begin s<=1;t<=0;end   1:if(rxd==0)begin s<=2;t<=t+1;end  2:if(t==6)  begin  if(rxd==0)    begin s<=3;t<=0;error<=0;end  else    begin s<=1;t<=0; end  endelse t<=t+1;  3:if(t==11)    begindata0[0]<=rxd;t<=0;s<=4;end else t<=t+1;  4:if(t==11)    begin data0[1]<=rxd;t<=0;s<=5;end  else t<=t+1;  5:if(t==11)    begindata0[2]<=rxd;t<=0;s<=6;end else t<=t+1;  6:if(t==11)    begindata0[3]<=rxd;t<=0;s<=7;end else t<=t+1;  7:if(t==11)    begindata0[4]<=rxd;t<=0;s<=8;end else t<=t+1;  8:if(t==11)    begindata0[5]<=rxd;t<=0;s<=9;end else t<=t+1;  9:if(t==11)    begindata0[6]<=rxd;t<=0;s<=10;end else t<=t+1;  10:if(t==11)    begindata0[7]<=rxd;t<=0;s<=11;end else t<=t+1;  11:if(t==11)       if(rxd==1)          begin t<=0;s<=0;data1<=data0;error<=0;          rdc<=1; //receive data completed          end       else          begin error<=1;t<=0;s<=0;end//frame  error or overflow error    else        t<=t+1; default:begin t<=0;s<=0;end endcaseendendmodule