PS2键盘时钟与系统时钟

2019-07-16 01:27发布

请问一下,在编写ps2键盘程序时,键盘的时钟和系统时钟是什么关系????
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6条回答
shangwfa
1楼-- · 2019-07-16 06:11
没有任何关系,键盘的时钟是我们采集键盘数据输出的依据
yoonssica
2楼-- · 2019-07-16 11:19
shangwfa 发表于 2013-7-29 23:48
没有任何关系,键盘的时钟是我们采集键盘数据输出的依据

也就是说数据只与键盘的时钟有关,而与系统的是时钟无关?那系统时钟做什么用呢?
主宰自己
3楼-- · 2019-07-16 14:19
不用管他,板子上有,你直接在顶层模块输入键盘时钟就好了
yoonssica
4楼-- · 2019-07-16 19:05
主宰自己 发表于 2013-7-30 12:32
不用管他,板子上有,你直接在顶层模块输入键盘时钟就好了

  1. <DIV class=blockcode>
  2. <BLOCKQUOTE>library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;

  6. entity ps2 is
  7. port (resetn: in std_logic; -- active low reset
  8. clock: in std_logic; -- system clock
  9. ps2_clk: in std_logic; -- PS/2 clock line
  10. ps2_dta: in std_logic; -- PS/2 data line
  11. hit_1: out std_logic;
  12. ascii: out std_logic_vector(7 downto 0)); -- LED outputs
  13. end ps2;

  14. architecture behavioral of ps2 is
  15. type state_type is (IDLE, START, DATA, PARITY); -- FSM states
  16. signal ps2_dv: std_logic; -- PS/2 data valid
  17. signal prv_ps2_clk, act_ps2_clk: std_logic; -- auxiliary signals
  18. signal recdata: std_logic_vector(7 downto 0); -- read data
  19. signal shift: std_logic; -- enable for shift reg.
  20. signal n_shift: std_logic; -- auxiliary signal
  21. signal latch: std_logic; -- latch read data
  22. signal n_latch: std_logic; -- auxiliary signal
  23. signal err: std_logic; -- parity or stop error
  24. signal n_err: std_logic; -- auxiliary signal
  25. signal parset: std_logic; -- preset for parity check
  26. signal n_parset: std_logic; -- auxiliary signal
  27. signal c_state, n_state: state_type; -- current & next states
  28. signal cntval: std_logic_vector(2 downto 0); -- counter of data bits
  29. signal zero: std_logic; -- counter is zero
  30. signal parbit: std_logic; -- odd parity of data
  31. signal leds:std_logic_vector(7 downto 0);
  32. signal hit_cnt:std_logic_vector(8 downto 0);
  33. signal hit:std_logic;
  34. begin
  35. -- Provides a one-shot pulse after every falling edge of PS/2 clock
  36. PS_CLK_SYNC: process(clock, resetn)
  37. begin
  38. if (resetn = '0') then
  39. prv_ps2_clk <= '1';
  40. act_ps2_clk <= '1';
  41. elsif (clock'event and clock = '1') then
  42. act_ps2_clk <= ps2_clk;
  43. prv_ps2_clk <= act_ps2_clk;
  44. end if;
  45. end process;
  46. ps2_dv <= (not act_ps2_clk) and prv_ps2_clk;

  47. -- Serial input, parallel output shift register
  48. SIPO: process(clock, resetn)
  49. begin
  50. if (resetn = '0') then
  51. recdata <= (others => '0');
  52. elsif (clock'event and clock = '1') then
  53. if (shift = '1') then
  54. recdata <= ps2_dta & recdata(7 downto 1);
  55. end if;
  56. end if;
  57. end process;

  58. -- Counter of data bits
  59. COUNT8: process(resetn, clock)
  60. begin
  61. if (resetn = '0') then
  62. cntval <= (others => '0');
  63. elsif (clock'event and clock = '1') then
  64. if (shift = '1') then
  65. cntval <= cntval + 1;
  66. end if;
  67. end if;
  68. end process;
  69. zero <= not (cntval(0) or cntval(1) or cntval(2));

  70. -- Parity check of received data
  71. PARITY_CHECK: process(clock, parset)
  72. begin
  73. if (parset = '1') then
  74. parbit <= '1';
  75. elsif (clock'event and clock = '1') then
  76. if (shift = '1' and ps2_dta = '1') then
  77. parbit <= not parbit;
  78. end if;
  79. end if;
  80. end process;

  81. -- Synchronous process of control state machine
  82. FSM_SYNC: process(clock, resetn)
  83. begin
  84. if (resetn = '0') then
  85. c_state <= IDLE;
  86. shift <= '0';
  87. latch <= '0';
  88. err <= '0';
  89. parset <= '1';
  90. elsif (clock'event and clock = '1') then
  91. c_state <= n_state;
  92. shift <= n_shift;
  93. latch <= n_latch;
  94. err <= n_err;
  95. parset <= n_parset;
  96. end if;
  97. end process;

  98. -- Combinatorial process of control state machine
  99. FSM_COMB: process(c_state, ps2_dv, ps2_dta, zero)
  100. begin -- default values
  101. n_shift <= '0';
  102. n_latch <= '0';
  103. n_err <= '0';
  104. n_parset <= '0';
  105. case c_state is -- wait to receive data
  106. when IDLE => if ((ps2_dv and (not ps2_dta)) = '1') then
  107. n_state <= START;
  108. n_parset <= '1';
  109. else
  110. n_state <= IDLE;
  111. end if;
  112. -- receive first data bit
  113. when START => if (ps2_dv = '0') then
  114. n_state <= START;
  115. else
  116. n_state <= DATA;
  117. n_shift <= '1';
  118. end if;
  119. -- receive remaining data bits and parity
  120. when DATA => if (ps2_dv = '0') then
  121. n_state <= DATA;
  122. elsif (zero = '0') then
  123. n_state <= DATA;
  124. n_shift <= '1';
  125. else
  126. n_state <= PARITY;
  127. if (parbit /= ps2_dta) then
  128. n_err <= '1';
  129. end if;
  130. end if;
  131. -- receive stop bit
  132. when PARITY => if (ps2_dv = '0') then
  133. n_state <= PARITY;
  134. else
  135. n_state <= IDLE;
  136. n_latch <= '1';
  137. n_err <= not ps2_dta;
  138. end if;
  139. end case;
  140. end process;

  141. -- Output latch
  142. LED_OUTPUTS: process(resetn, clock)
  143. begin
  144. if (resetn = '0') then
  145. leds <= (others => '1');
  146. elsif (clock'event and clock = '1') then
  147. if (err = '1') then
  148. leds <= (others => '1');
  149. elsif (latch = '1') then
  150. leds <= recdata;
  151. end if;
  152. end if;
  153. end process;
  154. PROCESS(leds)
  155. BEGIN
  156. case leds is
  157. when "01000101"=> ascii <= "00110000"; hit<='1'; --0
  158. when "00010110"=> ascii <= "00110001"; hit<='1'; --1
  159. when "00011110"=> ascii <= "00110010"; hit<='1'; --2
  160. when "00100110"=> ascii <= "00110011"; hit<='1'; --3
  161. when "00100101"=> ascii <= "00110100"; hit<='1'; --4
  162. when "00101110"=> ascii <= "00110101"; hit<='1'; --5
  163. when "00110110"=> ascii <= "00110110"; hit<='1'; --6
  164. when "00111101"=> ascii <= "00110111"; hit<='1'; --7
  165. when "00111110"=> ascii <= "00111000"; hit<='1'; --8
  166. when "01000110"=> ascii <= "00111001"; hit<='1'; --9
  167. when "00011100"=> ascii <= "01100001"; hit<='1'; --a
  168. when "00110010"=> ascii <= "01100010"; hit<='1'; --b
  169. when "00100001"=> ascii <= "01100011"; hit<='1'; --c
  170. when "00100011"=> ascii <= "01100100"; hit<='1'; --d
  171. when "00100100"=> ascii <= "01100101"; hit<='1'; --e
  172. when "00101011"=> ascii <= "01100110"; hit<='1'; --f
  173. when "00110100"=> ascii <= "01100111"; hit<='1'; --g
  174. when "00110011"=> ascii <= "01101000"; hit<='1'; --h
  175. when "01000011"=> ascii <= "01101001"; hit<='1'; --i
  176. when "00111011"=> ascii <= "01101010"; hit<='1'; --j
  177. when "01000010"=> ascii <= "01101011"; hit<='1'; --k
  178. when "01001011"=> ascii <= "01101100"; hit<='1'; --l
  179. when "00111010"=> ascii <= "01101101"; hit<='1'; --m
  180. when "00110001"=> ascii <= "01101110"; hit<='1'; --n
  181. when "01000100"=> ascii <= "01101111"; hit<='1'; --o
  182. when "01001101"=> ascii <= "01110000"; hit<='1'; --p
  183. when "00010101"=> ascii <= "01110001"; hit<='1'; --q
  184. when "00101101"=> ascii <= "01110010"; hit<='1'; --r
  185. when "00011011"=> ascii <= "01110011"; hit<='1'; --s
  186. when "00101100"=> ascii <= "01110100"; hit<='1'; --t
  187. when "00111100"=> ascii <= "01110101"; hit<='1'; --u
  188. when "00101010"=> ascii <= "01110110"; hit<='1'; --v
  189. when "00011101"=> ascii <= "01110111"; hit<='1'; --w
  190. when "00100010"=> ascii <= "01111000"; hit<='1'; --x
  191. when "00110101"=> ascii <= "01111001"; hit<='1'; --y
  192. when "00011010"=> ascii <= "01111010"; hit<='1'; --z
  193. when "00111001"=> ascii <= "00100000"; hit<='1'; --spacebar
  194. when "01100110"=> ascii <= "00100000"; hit<='1'; --backspace
  195. when "01110001"=> ascii <= "11100000"; hit<='1'; --del
  196. when others => ascii <= "00100000"; hit<='0'; --' ' for unlisted characters.
  197. end case;
  198. if hit='1' then
  199. if hit_cnt="111111111" then
  200. hit_1<='1';
  201. hit_cnt<="000000000";
  202. else
  203. hit_cnt<=hit_cnt+1;
  204. end if;
  205. else
  206. hit_1<=hit;
  207. end if;
  208. END PROCESS;

  209. end behavioral;
复制代码这个程序里的 if (resetn = '0') then
prv_ps2_clk <= '1';
act_ps2_clk <= '1';
elsif (clock'event and clock = '1') then
act_ps2_clk <= ps2_clk;
prv_ps2_clk <= act_ps2_clk;
end if;

这个部分我不能理解,为什么是时钟的上升沿的时候进行那些操作???

shangwfa
5楼-- · 2019-07-16 20:32
 精彩回答 2  元偷偷看……
yoonssica
6楼-- · 2019-07-17 01:48
shangwfa 发表于 2013-8-28 12:28
当然有用了,可以用于键盘的解码

这。。。。。。。。。。。

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