FPGA控制DDS输出调频信号时，频谱仪上只出来一个下限值（...

2019-07-16 01:29发布

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FPGA型号EP1C3T144I7N，配置芯片型号EPC2LI20N，DDS型号AD9910，用Quartus II软件编程下载，JATG模式，程序很简单，只是采用DRG模式输出一个调频信号，但是我的输出结果只有一个下限值（正斜率调频，负斜率调频时只出现上限值），感觉好像是没跳起来，但是我用示波器检查调频dds_ctrl信号和io_update信号是对的，有上升沿的作用，请教大神指导一下，这种情况是怎么回事？？
附注：加入点频模式程序时，输出是正确的。
原理图如下和程序代码：
tica, arial">library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;--------------------------------------------------------------------entity Set_Data_DDS_T isport(clk_ref :in  std_logic;P_Data    :out std_logic_vector(71 downto 0);flag    :out std_logic_vector(1 downto 0);ena :out std_logic;clr :out std_logic;dds_ctrl :out std_logic;io_update  :out std_logic;io_rst    :out std_logic);end Set_Data_DDS_T;architecture Set_Data_body of Set_Data_DDS_T is
--constant CFR1_APA    :std_logic_vector(71 downto 0) := x"00_0000_2000_0000_0000"; ---Autoclear phase accumulator constant CFR1          :std_logic_vector(71 downto 0) := x"00_0000_0000_0000_0000"; constant CFR2_DRG_ON :std_logic_vector(71 downto 0) := x"01_004C_0820_0000_0000"; ---Enable SYNC_CLK and DRG, no-dwell HIGH--constant CFR2_DRG_OFF :std_logic_vector(71 downto 0) := x"01_0040_0820_0000_0000"; ---Enable SYNC_CLK and disable DRGconstant CFR3          :std_logic_vector(71 downto 0) := x"02_1F3F_C000_0000_0000"; ---REFCLK input divider bypass  constant DAC          :std_logic_vector(71 downto 0) := x"03_0000_00FF_0000_0000"; constant LSRR          :std_logic_vector(71 downto 0) := x"0D_0001_0001_0000_0000"; --0X0D,FIXED, DRG rate constant LSPR_ON       :std_logic_vector(71 downto 0) := x"0B_3355_5555_28AA_AAAB"; ---0x0B, DRG limit, freq range 152.5-192.5MHzconstant LSPR_OFF    :std_logic_vector(71 downto 0) := x"0B_0000_0000_0000_0000"; ---0x0B, no signal output constant LSDPR       :std_logic_vector(71 downto 0) := x"0C_0000_48D1_0000_48D1"; ---0x0C, DRG frequency step beginprocess(clk_ref)variable count :integer range 0 to 18000;beginif(clk_ref'event and clk_ref='1')thenif count<8000 then    count:=count+1;
---reset the i/o---if count=5 then          io_update<='0';          io_rst <='0';          dds_ctrl <='0';       elsif count=7 then  io_rst <='1';elsif count=10 then  io_rst <='0';
---Send CFR1--------------elsif count=20 thenflag<="01";elsif count=25 thenP_Data<=CFR1;clr<='1';elsif count=27 thenclr<='0';       elsif count=30 thenena<='1';elsif count=130 thenena<='0';---Send CFR2_DRG_ON--------------elsif count=155 thenP_Data<=CFR2_DRG_ON;clr<='1';elsif count=157 thenclr<='0';       elsif count=160 thenena<='1';elsif count=260 thenena<='0';---Send CFR3--------------elsif count=285 thenP_Data<=CFR3;clr<='1';elsif count=287 thenclr<='0';       elsif count=290 thenena<='1';elsif count=390 thenena<='0';---Send DAC--------------elsif count=415 thenP_Data<=DAC;clr<='1';elsif count=417 thenclr<='0';       elsif count=420 thenena<='1';elsif count=520 thenena<='0';---Send LSPR_ON--------------elsif count=540 thenflag<="00";elsif count=545 thenP_Data<=LSPR_ON;clr<='1';elsif count=547 thenclr<='0';       elsif count=550 thenena<='1';elsif count=750 thenena<='0';---Send LSDPR--------------elsif count=775 thenP_Data<=LSDPR;clr<='1';elsif count=777 thenclr<='0';       elsif count=780 thenena<='1';elsif count=980 thenena<='0';---Send LSRR--------------elsif count=1000 thenflag<="01";elsif count=1005 thenP_Data<=LSRR;clr<='1';elsif count=1007 thenclr<='0';       elsif count=1010 thenena<='1';elsif count=1110 thenna<='0';
---Update the previous registers and start FM-----elsif count =1114 thenio_update <='1';    --update the register from the buffer;elsif count=1118 then       dds_ctrl <='1';elsif count=1126 thenio_update <='0';elsif count=1138 thendds_ctrl <='0';end if;    elseP_Data<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";count :=0;    end if;
end if;end process;end Set_Data_body;