always @(posedge count[17])
begin
dout1 <= key_in;
dout2 <= dout1;
dout3 <= dout2;
end
always @(posedge clk)
begin
count<=count+1'b1;
if(count==22'd2500000)
begin
count<=22'd0;
ms = ~ms;
end
end
always @(negedge key_done[1])
begin
keyen = ~keyen;
end
always @(posedge ms)
begin
if(!key_done[0])
counter<=16'd0;
else if(!keyen)
begin
counter[3:0]<=counter+1'b1;
if(counter[3:0]==4'h9)
begin
counter[3:0]<=4'd0;
counter[7:4]<=counter[7:4]+1'b1;
if(counter[7:4]==4'h9)
begin
counter[7:4]<=4'd0;
counter[11:8]<=counter[11:8]+1'b1;
if(counter[11:8]==4'h9)
begin
counter[11:8]<=4'd0;
counter[15:12]<=counter[15:12]+1'b1;
if(counter[15:12]==4'h9)
begin
counter[15:12]<=4'd0;
end
end
end
end
end
end
input clk;
input [1:0] key_in;
output [7:0] sm_seg;
output [3:0] sm_bit;
reg ms,keyen;
reg [3:0] sm_bit_reg;
reg [7:0] sm_seg_reg;
reg [15:0]counter;
reg [21:0] count;
reg [7:0] dis_dat;
reg [1:0] dout1,dout2,dout3;
wire[1:0] key_done;
wire [3:0] sm_bit;
wire [7:0] sm_seg;
assign sm_bit = sm_bit_reg;
assign sm_seg = sm_seg_reg;
assign key_done = (dout1 | dout2 | dout3);
always @(posedge count[17])
begin
dout1 <= key_in;
dout2 <= dout1;
dout3 <= dout2;
end
always @(posedge clk)
begin
count<=count+1'b1;
if(count==22'd2500000)
begin
count<=22'd0;
ms = ~ms;
end
end
always @(negedge key_done[1])
begin
keyen = ~keyen;
end
always @(posedge ms)
begin
if(!key_done[0])
counter<=16'd0;
else if(!keyen)
begin
counter[3:0]<=counter+1'b1;
if(counter[3:0]==4'h9)
begin
counter[3:0]<=4'd0;
counter[7:4]<=counter[7:4]+1'b1;
if(counter[7:4]==4'h9)
begin
counter[7:4]<=4'd0;
counter[11:8]<=counter[11:8]+1'b1;
if(counter[11:8]==4'h9)
begin
counter[11:8]<=4'd0;
counter[15:12]<=counter[15:12]+1'b1;
if(counter[15:12]==4'h9)
begin
counter[15:12]<=4'd0;
end
end
end
end
end
end
always @(posedge clk)
begin
case(count[17:16])
2'd0:sm_bit_reg<=4'b1110;
2'd1:sm_bit_reg<=4'b1101;
2'd2:sm_bit_reg<=4'b1011;
2'd3:sm_bit_reg<=4'b0111;
default:sm_bit_reg<=4'b0000;
endcase
case(count[17:16])
2'd0:dis_dat<=counter[3:0];
2'd1:dis_dat<=counter[7:4];
2'd2:dis_dat<=counter[11:8];
2'd3:dis_dat<=counter[15:12];
default:dis_dat<=4'd0;
endcase
end
always @(posedge clk)
begin
case(dis_dat)
4'h0 : sm_seg_reg = 8'hc0; // "0"
4'h1 : sm_seg_reg = 8'hf9; // "1"
4'h2 : sm_seg_reg = 8'ha4; // "2"
4'h3 : sm_seg_reg = 8'hb0; // "3"
4'h4 : sm_seg_reg = 8'h99; // "4"
4'h5 : sm_seg_reg = 8'h92; // "5"
4'h6 : sm_seg_reg = 8'h82; // "6"
4'h7 : sm_seg_reg = 8'hf8; // "7"
4'h8 : sm_seg_reg = 8'h80; // "8"
4'h9 : sm_seg_reg = 8'h90; // "9"
default:sm_seg_reg<=8'hff;
endcase
if(count[17:16]==2'd1)
sm_seg_reg<=8'b0xxx_xxxx;
end
endmodule
参考然后自己修改一下看看咯
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