library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
en
tity mux1_8 is
port (
SEL : in std_logic_vector( 3 downto 0);
DATA_IN : in std_logic_vector( 7 downto 0) ;
F : OUT std_logic_vector( 31 downto 0);
P : OUT std_logic_vector( 9 downto 0));
end mux1_8;
architecture behav of mux1_8 is
begin
PROCESS(SEL,DATA_IN)
BEGIN
IF SEL="1000" THEN
F(31 DOWNTO 0) <= "00000000000000000000000000000000";
P(9 DOWNTO 0) <= "0000000000";
ELSIF SEL="1001" THEN
F(7 DOWNTO 0) <= DATA_IN(7 DOWNTO 0);
ELSIF SEL="1010" THEN
F(15 DOWNTO 8)<= DATA_IN(7 DOWNTO 0);
ELSIF SEL="1011" THEN
F(23 DOWNTO 16)<= DATA_IN(7 DOWNTO 0);
ELSIF SEL="1100" THEN
F(31 DOWNTO 24) <= DATA_IN(7 DOWNTO 0);
ELSIF SEL="1101" THEN
P(7 DOWNTO 0) <= DATA_IN(7 DOWNTO 0);
ELSIF SEL="1110" THEN
P(9 DOWNTO 8) <= DATA_IN(1 DOWNTO 0);
END IF ;
END PROCESS;
end;
小弟语法不好,小小的程序,编译出来就老是waring:
Warning: Latch FWORD[16]$latch has unsafe behavior
Warning: Ports ENA and CLR on the latch are fed by the same signal SEL[0]
实在搞不懂呀,怎么能避免latch长生呀?
怎么知道 latch有没有相同的信号提供给不同端口的门闩,还有怎么删除latch呀
望
FPGA大佬帮指点一下!多谢了!!
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