always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
cnt <= 0;
end
else if(cnt < (32768000 - 1)) begin
cnt <= cnt + 1;
end
else begin
cnt <= 0;
end
end
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
led <= 0;
end
else if(cnt == (32768000 - 1) ) begin
led <= led + 1;
end
else ;
end
reg [28:0] cnt;
reg [1:0] led;
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
cnt <= 0;
end
else if(cnt < (32768000 - 1)) begin
cnt <= cnt + 1;
end
else begin
cnt <= 0;
end
end
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
led <= 0;
end
else if(cnt == (32768000 - 1) ) begin
led <= led + 1;
end
else ;
end
猿来还是要靠计数器啊。。。我还是重新弄个分频模块好了。。。其他地方也能用~谢了~
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