关于 3-8译码器的 vhdl描述问题

2019-07-16 02:03发布

分别使用Process语句、when-else语句和case-when语句完成3-8译码器的设计。
本人初学,希望大家帮我看下,我写的程序
  1. Library ieee
  2. Use ieee.std_logic_1164.all
  3. Entity decoder3_8 is
  4.    Port(  a,b,c:in std_logic;
  5.          y:out std logic_vector(7 down to 0);
  6.    );
  7. Architecture art of decoder3_8 is
  8.    Signal s:std_logic_vector(2 down to 0);
  9.    S<=a&b&c;
  10. Begin
  11.    Process(a,b,c)  is
  12.       
  13.       Begin
  14.          If s=”000 “ then
  15.            y<=”00000001”;
  16.          Elseif s=”001” then
  17.            Y<=”00000010”;
  18.          Elseif s=”010” then
  19.            Y<=”00000100”;
  20.          Elseif s=”011” then
  21.            Y<=”00001000”;
  22.          Elseif s=”100” then
  23.            Y<=”00010000”;

  24.            
  25.          Elseif s=”101” then
  26.            Y<=”00100000”;
  27.          Elseif s=”110” then
  28.            Y<=”01000000”;
  29.          Elseif s=”111” then
  30.            Y<=”10000000”;
  31.      Else
  32.           Y=”00000000”;
  33.    End if;
  34. End process;
  35. End architecture art ;

  36. //

  37. Library ieee
  38. Use ieee.std_logic_1164.all
  39. Entity decoder3_8 is
  40.    Port(  a,b,c:in std_logic;
  41.          y:out std logic_vector(7 down to 0);
  42.    );
  43. Architecture art of decoder3_8 is
  44.    Signal s:std_logic_vector(2 down to 0);
  45.    S<=a&b&c;
  46.    Begin
  47.   Y(7 down to  0)<=”00000001” When s=”001” else
  48.      ”00000010” When s=”001” else
  49.      ”00000100” When s=”001” else
  50.      ”00001000” When s=”001” else
  51.      ”00010000” When s=”001” else
  52.      ”00100000” When s=”001” else
  53.      ”0100000” When s=”001” else
  54.        ”10000000” When s=”001” else
  55.        “00000000”;
  56. End architecture art;



  57. // Library ieee
  58. Use ieee.std_logic_1164.all
  59. Entity decoder3_8 is
  60.    Port(  a,b,c:in std_logic;
  61.          y:out std logic_vector(7 down to 0);
  62.    );
  63. Architecture art of decoder3_8 is
  64.    Signal s:std_logic_vector(2 down to 0);
  65.    S<=a&b&c;
  66. Case s is
  67. When "000"=> y<="00000001";
  68. When "001"=> y<="00000010";
  69. When "010"=> y<="00000100";
  70. When "011"=> y<="00001000";
  71. When "100"=> y<="00010000";
  72. When "101"=> y<="00100000";
  73. When "110"=> y<="01000000";
  74. When "111"=> y<="10000000";
  75. When others=> y<="00000000";
  76. End case;
  77. End architecture art ;
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