A=1,A1=0,B=0,;
A=0,A1=1,B=1;
B=1,B1=0,A=1;
B=0,B1=1,A=0;
A=1,A1=0,B=1;
A=0,A1=1,B=0;
B=1,B1=0,A=0;
B=0,B1=1,A=1;
CONT:PROCESS(CLK,RESET);
BEGIN
IF RESET='0' THEN
CONT16<=(OTHERS=>'0');
   ELSIF CLK'EVENT AND CLK=‘1’OR
IF
(A='1' AND  A1='0'  AND  B='0') OR
(A='0' AND  A1='1'  AND  B='1') OR
(B='1' AND  B1='0'  AND  A='1') OR
(B='0' AND  B1='1'  AND  A='0')
THEN CONT16<=CONT16+1;
ELSIF
(A='1' AND A1='0' AND B='1')OR
(A='0' AND A1='1' AND B='0')OR
(B='1' AND B1='0' AND A='0')OR
(B='0' AND B1='1' AND A='1')
THEN CONT16<=CONT16-1;
ELSE NULL;
END IF;
END IF;
END PROCESS;
LOCKC:PROCESS(RESET,LOCK);
BEGIN
IF(RESET='0')THEN
   OUT_LOCK<=(OTHERS=>'0');
ELSIF RISING_EDGE(LOCK) THEN;
  OUT_LOCK<=OUT_TMP;
ELSE NULL;
END IF;
END PROCESS;
CHOOSE:PROCESS(RESET,CLK);
BEGIN
IF(REST="0")THEN
     OUTPUT8<=(OTHERS=>'0');
   ELSIF(CHOOSE='0' AND CHOOSE_ONE='1') THEN
             OUTPUT8<=OUT_LOCK(7 DOWNTO 0);
ELSE NULL;
END IF;
END NULL;
END IF;
END PROCESS;

不懂   有  verilog  的吗