The Cause: This is actually a known issue and has been confirmed by the factory as a bug (in F54xx & 54xxA). It should be on forthcoming errata when the next revision of the document is released. The following are possible workarounds:
1. Use a GPIO pin as a chip select (CS) when the MSP430 is receiving data. In the Port ISR, switch the polarity on the interrupt pin edge select, enable the UART and RX interrupt, complete the UART transactions, and go back to sleep on the following GPIO interrupt request (release of the CS).
2. Enter LPM3 mode with SMCLKREQEN = 0, use a GPIO pin as a CS pin and, in the port ISR switch the polarity on the interrupt pin edge select, enable SMCLKREQEN bit, complete the UART transactions, and clear the SMCLKREQEN bit on the following GPIO interrupt request (release of the CS).
Both have an inherent latency between CS signal toggling and the MSP430 being able to receive data successfully, which should be accounted for by a delay on the master between toggling the CS signal and transmitting the first data byte. Else, one would still need to calculate the latency in respect to the baudrate and see how many bytes need to be re-sent from the master as to not lose any data. This case would reduce complexity on the master implementation by eliminating the critical timing from CS -> delay -> 1st TX byte.
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1. Use a GPIO pin as a chip select (CS) when the MSP430 is receiving data. In the Port ISR, switch the polarity on the interrupt pin edge select, enable the UART and RX interrupt, complete the UART transactions, and go back to sleep on the following GPIO interrupt request (release of the CS).
2. Enter LPM3 mode with SMCLKREQEN = 0, use a GPIO pin as a CS pin and, in the port ISR switch the polarity on the interrupt pin edge select, enable SMCLKREQEN bit, complete the UART transactions, and clear the SMCLKREQEN bit on the following GPIO interrupt request (release of the CS).
Both have an inherent latency between CS signal toggling and the MSP430 being able to receive data successfully, which should be accounted for by a delay on the master between toggling the CS signal and transmitting the first data byte. Else, one would still need to calculate the latency in respect to the baudrate and see how many bytes need to be re-sent from the master as to not lose any data. This case would reduce complexity on the master implementation by eliminating the critical timing from CS -> delay -> 1st TX byte.
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