timescale 1ns/100ps
module Data_SCRAM_tb;
wire [7:0] Data_out;
wire k_flag;
reg[7:0] Data_in;
reg clk,rst;
initial
begin
clk=0;
rst=0;
#2 rst=1;
#1000
$stop();
end
always #1 clk=~clk;
always @(posedge clk or negedge rst)
begin
if(!rst)
Data_in<=8'b00000000;
else
Data_in<=Data_in+8'b00000001;
end
Data_SCRAM Dtest(Data_in,Data_out,clk,rst,k_flag);
endmodule
run gate-level
# ** Error: (vsim-3053) E:/Quartus1/raoma/Data_SCRAM_tb.v(23): Illegal output or inout port connection for "port 'Data_out'".
# Region: /Data_SCRAM_tb/Dtest
module Data_SCRAM_tb;
wire [7:0] Data_out;
wire k_flag;
reg[7:0] Data_in;
reg clk,rst;
initial
begin
clk=0;
rst=0;
#2 rst=1;
#1000
$stop();
end
always #1 clk=~clk;
always @(posedge clk or negedge rst)
begin
if(!rst)
Data_in<=8'b00000000;
else
Data_in<=Data_in+8'b00000001;
end
Data_SCRAM Dtest(Data_in,Data_out,clk,rst,k_flag);
endmodule
run gate-level
# ** Error: (vsim-3053) E:/Quartus1/raoma/Data_SCRAM_tb.v(23): Illegal output or inout port connection for "port 'Data_out'".
# Region: /Data_SCRAM_tb/Dtest
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