Two reset pins are provided for independent control of half-bridges A/B and C/D. When RESET_AB is asserted low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance (Hi-Z) state. Likewise, asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high- impedance state.



主要请问，这里的低电平后，使得场相应管就变成高阻状态，这里的高阻状态指的是什么意思？ 此帖出自小平头技术问答