// On TMX samples, to get the best performance of on chip RAM blocks M0/M1/L0/L1/H0 internal
// control registers bit have to be enabled. The bits are in Device emulation registers.
DevEmuRegs.M0RAMDFT = 0x0300;
DevEmuRegs.M1RAMDFT = 0x0300;
DevEmuRegs.L0RAMDFT = 0x0300;
DevEmuRegs.L1RAMDFT = 0x0300;
DevEmuRegs.H0RAMDFT = 0x0300;
// Initalize PLL
SysCtrlRegs.PLLCR = 0xA;
// Wait for PLL to lock
for(i= 0; i< 5000; i++){}
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
SysCtrlRegs.HISPCP.all = 0x0001;
SysCtrlRegs.LOSPCP.all = 0x0002;
// Peripheral clock enables set for the selected peripherals.
SysCtrlRegs.PCLKCR.bit.EVAENCLK=1;
SysCtrlRegs.PCLKCR.bit.EVBENCLK=1;
// SysCtrlRegs.PCLKCR.bit.SCIENCLKA=1;
// SysCtrlRegs.PCLKCR.bit.SCIENCLKB=1;
SysCtrlRegs.PCLKCR.bit.ADCENCLK=1;
{
Uint16 i;
EALLOW;
// On TMX samples, to get the best performance of on chip RAM blocks M0/M1/L0/L1/H0 internal
// control registers bit have to be enabled. The bits are in Device emulation registers.
DevEmuRegs.M0RAMDFT = 0x0300;
DevEmuRegs.M1RAMDFT = 0x0300;
DevEmuRegs.L0RAMDFT = 0x0300;
DevEmuRegs.L1RAMDFT = 0x0300;
DevEmuRegs.H0RAMDFT = 0x0300;
// Disable watchdog module
SysCtrlRegs.WDCR= 0x0068;
// Initalize PLL
SysCtrlRegs.PLLCR = 0xA;
// Wait for PLL to lock
for(i= 0; i< 5000; i++){}
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
SysCtrlRegs.HISPCP.all = 0x0001;
SysCtrlRegs.LOSPCP.all = 0x0002;
// Peripheral clock enables set for the selected peripherals.
SysCtrlRegs.PCLKCR.bit.EVAENCLK=1;
SysCtrlRegs.PCLKCR.bit.EVBENCLK=1;
// SysCtrlRegs.PCLKCR.bit.SCIENCLKA=1;
// SysCtrlRegs.PCLKCR.bit.SCIENCLKB=1;
SysCtrlRegs.PCLKCR.bit.ADCENCLK=1;
EDIS;
}
看看系统初始化中的SysCtrlRegs.PCLKCR.bit.ADCENCLK=1; ADC时钟是否使能
那应该是配置的问题了
void InitAdc(void)
{
unsigned int i;
AdcRegs.ADCTRL1.bit.RESET=1;
NOP;
AdcRegs.ADCTRL1.bit.RESET=0;
AdcRegs.ADCTRL1.bit.SUSMOD=3;
AdcRegs.ADCTRL1.bit.ACQ_PS=0;
AdcRegs.ADCTRL1.bit.CPS=0;
AdcRegs.ADCTRL1.bit.CONT_RUN=0;
AdcRegs.ADCTRL1.bit.SEQ_CASC=1;
AdcRegs.ADCTRL3.bit.ADCBGRFDN=3;
for(i=0;i<10000;i++) NOP;
AdcRegs.ADCTRL3.bit.ADCPWDN=1;
for(i=0;i<5000;i++) NOP;
AdcRegs.ADCTRL3.bit.ADCCLKPS=10;
AdcRegs.ADCTRL3.bit.SMODE_SEL=1;
AdcRegs.MAX_CONV.bit.MAX_CONV=7;//15;
AdcRegs.CHSELSEQ1.bit.CONV00=0;
AdcRegs.CHSELSEQ1.bit.CONV01=1;
AdcRegs.CHSELSEQ1.bit.CONV02=2;
AdcRegs.CHSELSEQ1.bit.CONV03=3;
AdcRegs.CHSELSEQ2.bit.CONV04=4;
AdcRegs.CHSELSEQ2.bit.CONV05=5;
AdcRegs.CHSELSEQ2.bit.CONV06=6;
AdcRegs.CHSELSEQ2.bit.CONV07=7;
/*
AdcRegs.CHSELSEQ3.bit.CONV08=8;
AdcRegs.CHSELSEQ3.bit.CONV09=9;
AdcRegs.CHSELSEQ3.bit.CONV10=10;
AdcRegs.CHSELSEQ3.bit.CONV11=11;
AdcRegs.CHSELSEQ4.bit.CONV12=12;
AdcRegs.CHSELSEQ4.bit.CONV13=13;
AdcRegs.CHSELSEQ4.bit.CONV14=14;
AdcRegs.CHSELSEQ4.bit.CONV15=15;
*/
AdcRegs.ADC_ST_FLAG.bit.INT_SEQ1_CLR=1;
AdcRegs.ADC_ST_FLAG.bit.INT_SEQ2_CLR=1;
AdcRegs.ADCTRL2.bit.EVB_SOC_SEQ=0;
AdcRegs.ADCTRL2.bit.RST_SEQ1=0;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1=1;
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1=0;
AdcRegs.ADCTRL2.bit.EVA_SOC_SEQ1=0;
AdcRegs.ADCTRL2.bit.EXT_SOC_SEQ1=0;
AdcRegs.ADCTRL2.bit.RST_SEQ2=0;
AdcRegs.ADCTRL2.bit.SOC_SEQ2=0;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2=0;
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ2=0;
AdcRegs.ADCTRL2.bit.EVB_SOC_SEQ2=0;
AdcRegs.ADCTRL2.bit.SOC_SEQ1=1;
}
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