初学者求助。根据原理图编写VHDL语言

1楼-- · 2019-07-18 19:10

单进程的case语句有错，将WHEN至END IF中的ST换成NST，既次态！

2楼-- · 2019-07-18 21:24

至于双进程的吗，请参考以下程序（我们课本上的）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY s_machine IS
  PORT ( clk,reset : IN STD_LOGIC;
      state_inputs : IN STD_LOGIC_VECTOR (0 TO 1);
      comb_outputs : OUT INTEGER RANGE 0 TO 15 );
END s_machine;
ARCHITECTURE behv OF s_machine IS
  TYPE FSM_ST IS (s0, s1, s2, s3);  --数据类型定义，状态符号化
  SIGNAL current_state, next_state: FSM_ST;--将现态和次态定义为新的数据类型
BEGIN
REG: PROCESS (reset,clk)                --主控时序进程

BEGIN
IF reset = '1' THEN current_state <= s0;--检测异步复位信号
ELSIF clk='1' AND clk'EVENT THEN
   current_state <= next_state;
END IF;
  END PROCESS;
COM:PROCESS(current_state, state_Inputs)    --主控组合进程
  BEGIN
CASE current_state IS
   WHEN s0 => comb_outputs<= 5;
      IF state_inputs = "00" THEN  next_state<=s0;
         ELSE  next_state<=s1;
      END IF;
   WHEN s1 =>  comb_outputs<= 8;
      IF state_inputs = "00" THEN  next_state<=s1;
      ELSE  next_state<=s2;
      END IF;
   WHEN s2 => comb_outputs<= 12;
      IF state_inputs = "11" THEN  next_state <= s0;
      ELSE  next_state <= s3;
      END IF;
   WHEN s3 =>  comb_outputs <= 14;
      IF state_inputs = "11" THEN  next_state <= s3;
      ELSE  next_state <= s0;
      END IF;
END case;
  END PROCESS;
END behv;